1. Field of the Invention
The invention is generally related to a method for providing planarized gate conductor on a substrate which includes both above-surface isolation and below-surface isolation, and to structures which result from the method.
2. Description of the Prior Art
Surface isolation techniques, such as "field-shield" isolation and "thick above-surface dielectric isolation", are used in semiconductor chip and wafer fabrication techniques to electronically isolate separate devices formed in a substrate. "Field-shield isolation" involves having a conducting layer insulated from the semiconductor or substrate. "Thick above-surface dielectric isolation" involves having a patterned, thick insulation layer (e.g., approximately 300 to 2500.ANG. thick) above the substrate.
These isolation techniques pose difficult problems for proper fabrication of gate conductor materials which must traverse over the above-surface isolation members. FIG. 1a shows a cross-sectional view of a gate conductor 10 on substrate 12 which traverses over isolation members 14, which can be field-shield isolation, thick dielectric isolation or any other above-surface isolation feature, and FIG. 1b shows a plan view of the gate conductor 10 passing over the isolation members 14 and the substrate 12. The cross-sectional view in FIG. 1a is taken along line A--A in FIG. 1b. The isolation members 14 project above the surface of substrate 12 and make the surface non-planar. This non-planarity is transferred to the deposited gate conductor material 10 at region 16 which is the site of the isolation/active area step.
The nonplanar characteristic of the substrate leads to several problems. First, because the substrate is non-planar, there may be depth of focus (DOF) problems in patterning the gate conductor 10 as well as other features in the active area. Specifically, photoresist (not shown) deposited on top of the gate conductor 10 will be thicker at region 16 than at regions above the isolation members 14. Thus, during photolithography, the photoresist will be exposed differently due to the variation in DOF. As is shown in FIG. 1b, the variation in exposure may ultimately lead to variations in the width of the gate conductor 10 at region 16. This width variation will adversely impact on the overall performance of the device due to shortening of the device channel. Second, gate conductor "stringers" 18, which are regions of gate conductor material not removed during etching of the gate conductor, may be formed along the edges of the active areas of substrate 12 due to the increase in the gate conductor thickness at the step from isolation region 14 to substrate region 12. The presence of stringers results in the shorts between adjacent gates.
As micro-electronics manufacturing progresses to smaller, more compact substrates with active areas separated by very little chip real estate, there is a need, when surface isolation techniques are utilized, to provide an effective means for preventing line width variation and stringer formation problems.